1. Field of the Invention
This invention relates to a semiconductor integrated circuit such as a semi-custom LSI (Large-Scale Integrated Circuit) designed by a gate-array technique or the like, and more particularly to a structure of capacitors formed in the semiconductor integrated circuit.
2. Description of the Related Art
In recent years, has been developed a semi-custom LSI in which a plurality of standard circuit elements are formed in advance on a semiconductor substrate and wirings are thereafter formed on the substrate to form a desired circuit. Since the circuit is obtained only by designing the layout of the wirings on a semiconductor substrate in which circuit elements are formed in a predetermined layout, the semi-custom LSI has some notable features of a short production period and a low manufacturing cost, compared to the conventional standard LSI in which both layouts of circuit elements and wirings are newly designed to form a circuit. The semi-custom LSI's are widely used to form logic circuits. Therefore, the LSI in which a plurality of logic gates are previously formed as the standard circuit elements are called a gate-array. The logic gates are called logic cells.
The gate-array will be further explained. A plurality of logic cells are first formed on a semiconductor substrate aligned in a number of parallel lines. The logic cells are wired to form a circuit with wiring layers disposed on space regions between the lines. In a case where it is necessary to control a timing of logic signal, the timing can be controlled by adding a capacitance to a specific wiring layer to give a time delay. In a course of the invention, the inventor devised a capacitor which is formed by adding an extended region to the wiring layer.
Usually, the wirings between logic cells are made by wiring layers formed on the space regions between the lines of logic gates. If the wiring layers are made of a single layer of wirings, the presence of the extended region apparently restricts a freedom of wiring design. In more practical case, the wiring layers are formed by use of two layers of wirings. A first layer is used for wirings running in a direction perpendicular to the lines of logic cells. A second layer is used for wirings running in parallel with the lines of logic cells. Since the extended region is added to a wiring formed by one of the two layers, the wiring freedom of the wirings used by the one of the two layers is restricted. The locations of interconnections between the wirings of the first layer and the wirings of the second layer are also restricted.
The extended regions are designed as a single region presenting a required capacitance. Therefore, the area of the extended region is individually determined. According to the gate-array technique, the wirings are automatically designed by use of a computer soft-ware. The individual design raises some problems in computer-aided designing (CAD). Additional programing is required to determine the area of the extended region. Furthermore, the extended region is formed in the same region as the wirings. The CAD must be programed to avoid overlapping of the extended region and other wirings.
Capacitances of the capacitors are affected by manufacture errors to change their value. If capacitances having a predetermined relationship are required, some adjustment of layout design is required to compensate the manufacture errors.